Dynamic RAM circuits commonly use a circuit known as a "booting circuit" to drive their wordlines in order to improve the DRAM performance. For example, U.S. Pat. No. 4,543,500 and 4,533,843 to McAlexander et al. contain disclosures of the advantages of booting the wordline of a DRAM above the supply voltage. Such booting circuits commonly produce a signal having two stages. In the first stage, the signal rises from a low voltage (ground) to a high voltage (the power supply voltage or "V.sub.cc "). When the signal reaches a threshold voltage V.sub.read, data from the DRAM cell addressed by the wordline may be read. It is desirable that the booting signal reach V.sub.read as quickly as possible in order to have a fast memory access time.
In the second stage of the signal, the signal is "booted" or "boosted" above V.sub.cc in order to fully restore the charge into the DRAM cell which was previously read. As taught by U.S. Pat. Nos. 4,533,843 and 4,543,500, to fully charge the cell, it is necessary to supply a voltage higher than V.sub.cc.
In previously developed booting circuits, an input signal undergoing a low to high transition is passed from the input to the output of the booting circuit, where it is used to generate the signal for the first stage. In such circuits, as the input signal is being passed to the output, a capacitor connected to the output is being charged by the output voltage. Subsequently, the charge stored in the capacitor is used to "boot" the output signal. Since the input signal is being used to charge the capacitor, the output signal for the first stage will be sloping, rather than being an abrupt low to high transition. Consequently, the time taken for the output signal to reach V.sub.read is increased relative to the input signal, and hence, the memory access time is often excessive in previously developed booting circuits.
Therefore, the need has arisen for a booting circuit having an output signal with a fast rising transition in order to produce faster memory access times.